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fn6957 rev 6.00 page 1 of 25 october 14, 2014 fn6957 rev 6.00 october 14, 2014 isl28134 5v ultra low noise, zero drift rail-to-rail precision op amp datasheet the isl28134 is a single, chopper-stabilized zero drift operational amplifier optimized for single and dual supply operation from 2.25v to 6.0v and 1.125v and 3.0v. the isl28134 uses auto-correction circuitry to provide very low input offset voltage, drift and a reduction of the 1/f noise corner below 0.1hz. the isl28134 achieves ultra low offset voltage, offset temperature drift, wide gain bandwidth and rail- to-rail input/output swing while minimizing power consumption. the isl28134 is ideal for amplifying the sensor signals of analog front-ends that include pressure, temperature, medical, strain gauge and inertial sensors down to the v levels. the isl28134 can be used over standard amplifiers with high stability across the industrial temperature range of -40c to +85c and the full industrial temperature range of -40c to +125c. the isl28134 is available in an industry standard pinout soic and sot-23 packages. applications ? medical instrumentation ?sensor gain amps ? precision low drift, low frequency adc drivers ? precision voltage reference buffers ? thermopile, thermocouple, and other temperature sensors front-end amplifiers ? inertial sensors ? process control systems ? weight scales and strain gauge sensors features ? rail-to-rail inputs and outputs - cmrr at v cm = 0.1v beyond v s . . . . . . . . . . . . . 135db, typ -v oh and v ol . . . . . . . . . . . . . . . . . . . . . . .10mv from v s , typ ? no 1/f noise corner down to 0.1hz - input noise voltage . . . . . . . . . . . . . . . . . 10nv/ ? hz at 1khz - 0.1hz to 10hz noise voltage . . . . . . . . . . . . . . . . . 250nv p-p ? low offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5v, max ? superb offset drift . . . . . . . . . . . . . . . . . . . . . . . 15nv/c, max ? single supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25v to 6.0v ? dual supply . . . . . . . . . . . . . . . . . . . . . . . . . 1.125v to 3.0v ?low i cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675a, typ ? wide bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5mhz ? operating temperature range - industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c - full industrial . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c ?packaging - single: soic, sot-23 related literature ? an1641 , ?isl28134soiceval1z evaluation board user?s guide? ? an1560 , ?making accurate voltage noise and current noise measurements on operational amplifiers down to 0.1hz? + - isl28134 isl26102 24-bit adc isl21010 5v vref +5 35 0 3 50 350 + - dcp isl22316 50k 50k 50 50 isl28134 figure 1. precision weigh scale / strain gauge figure 2. v os histogram v s = 5v number of amplifiers -2.0 -1.5 -1.0 -0.5 -2.5 0 200 400 600 800 1000 1200 0 0.5 1.0 1.5 2.0 2.5 1400 v s = 2.5v n = 2796 v cm = 0v t = -40c to +125c 1600
isl28134 fn6957 rev 6.00 page 2 of 25 october 14, 2014 pin configurations isl28134 (5 ld sot-23) top view isl28134 (8 ld soic) top view out v- in+ v+ in- 1 2 3 5 4 +- + - out v- in+ v+ in- 1 2 3 4 nc 8 7 6 5 nc nc pin descriptions isl28134 (8 ld soic) isl28134 (5 ld sot-23) pin name function equivalent circuit 2 4 in- inverting input (see circuit 1) 33in+non-inverting input circuit 1 42v-negative supply 61outoutput circuit 2 75v+positive supply 1, 5, 8 - nc no connect pin is floating. no connection made to ic. in- v+ in+ v- + - + - clock gen + drivers v+ v- out
isl28134 fn6957 rev 6.00 page 3 of 25 october 14, 2014 ordering information part number ( note 4 ) part marking temp range (c) package (pb-free) pkg. dwg. # isl28134ibz ( notes 1 , 3 ) 28134 ibz -40c to +85c 8 ld soic m8.15e isl28134fhz-t7 ( notes 2 , 3 )beea ( note 5 ) -40c to +125c 5 ld sot-23 p5.064a isl28134fhz-t7a ( notes 2 , 3 )beea ( note 5 ) -40c to +125c 5 ld sot-23 p5.064a ISL28134ISENSEV1Z evaluation board isl28134soiceval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requir ements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl28134 . for more information on msl please see techbrief tb363 . 5. the part marking is located on the bottom of the part.
isl28134 fn6957 rev 6.00 page 4 of 25 october 14, 2014 absolute maximum rating s thermal information supply voltage v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5v voltage vin to gnd. . . . . . . . . . . . . . . . . . . . . . . . (v- - 0.3v) to (v+ + 0.3v) v input differential voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma voltage vout to gnd (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(v+) or (v-) dv/dt supply slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100v/s esd rating human body model (tested per jed22-a114f) . . . . . . . . . . . . . . . . . 4kv machine model (tested per jed22-a115b). . . . . . . . . . . . . . . . . . . . 300v charged device model (tested per jed22-c110d) . . . . . . . . . . . . . . 2kv latch-up (passed per jesd78b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c thermal resistance (typical) ? ja (c/w) ? jc (c/w) 5 ld sot-23 ( notes 6 , 7 ) . . . . . . . . . . . . . . . 225 116 8 ld soic ( notes 6 , 7 ) . . . . . . . . . . . . . . . . . 125 77.2 maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 operating conditions ambient operating temperature range industrial grade package . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c full industrial grade package. . . . . . . . . . . . . . . . . . . . .-40c to +125c operating voltage range. . . . . . . . . . . . . . . . . 2.25v (1.125v) to 6v (3v) caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for ? jc , the ?case temp? location is taken at the package top center. electrical specifications v s = 5v, v cm = 2.5v, t a = +25c, unless otherwise specified . boldface limits apply across the specified operating temperature range. parameter description test conditions min ( note 8 )typ max ( note 8 )units dc specifications v os input offset voltage -2.5 -0.2 2.5 v t a = -40c to +85c -3.4 - 3.4 v t a = -40c to +125c -4 - -4 v tcv os input offset voltage temperature coefficient t a = -40c to +125c -15 -0.5 15 nv/c i b input bias current -300 120 300 pa t a = -40c to +85c -300 - 300 pa t a = -40c to +125c -550 - 550 pa tci b input bias current temperature coefficient t a = -40c to +85c - 1.4 - pa/c t a = -40c to +125c - 2 - pa/c i os input offset current -600 240 600 pa t a = -40c to +85c -600 - 600 pa t a = -40c to +125c -750 - 750 pa tci os input offset current temperature coefficient t a = -40c to +85c - 2.8 - pa/c t a = -40c to +125c - 4 - pa/c common mode input voltage range v+ = 5.0v, v- = 0v guaranteed by cmrr -0.1 - 5.1 v cmrr common mode rejection ratio v cm = -0.1v to 5.1v 120 135 - db v cm = -0.1v to 5.1v 115 --db psrr power supply rejection ratio v s = 2.25v to 6.0v 120 135 - db v s = 2.25v to 6.0v 120 --db v s supply voltage (v+ to v-) guaranteed by psrr 2.25 - 6.0 v
isl28134 fn6957 rev 6.00 page 5 of 25 october 14, 2014 i s supply current per amplifier r l = open - 675 900 a r l = open t a = -40c to +85c - - 1075 a r l = open t a = -40c to +125c - - 1150 a i sc short circuit output source current r l = short to v- - 65 - ma short circuit output sink current r l = short to v+ - -65 - ma v oh output voltage swing, high from v out to v + r l = 10k ? to v cm 15 10 - mv r l = 10k ? to v cm 15 --mv v ol output voltage swing, low from v - to v out r l = 10k ? to v cm - 10 15 mv r l = 10k ? to v cm -- 15 mv a ol open loop gain r l = 1m -174- db ac specifications c in input capacitance differential - 5.2 - pf common mode - 5.6 - pf e n input noise voltage f = 0.1hz to 10hz - 250 400 nv p-p f = 10hz - 8 - nv/ ? hz f = 1khz - 10 - nv/ ? hz i n input noise current f = 1khz - 200 - fa/ ? hz gbwp gain bandwidth product - 3.5 - mhz emirr emi rejection ratio a v = +1, v in = 200mv p-p , v cm = 0v, v+ = 2.5v, v- = -2.5v -75- db transient response sr positive slew rate v+ = 5v, v- = 0v, v out = 1v to 3v, r l = 100k , c l =3.7pf -1.5- v/s negative slew rate - 1.0 - v/s t r , t f , small signal rise time, t r 10% to 90% v+ = 5v, v- = 0v, v out = 0.1v p-p , r f = 0 , r l = 100k , c l =3.7pf -0.07- s fall time, t f 10% to 90% - 0.17 - s t r , t f large signal rise time, t r 10% to 90% v+ = 5v, v- = 0v, v out = 2v p-p , r f =0 , r l = 100k , c l =3.7pf -1.3- s fall time, t f 10% to 90% - 2.0 - s t s settling time to 0.1%, 2v p-p step a v = -1, r f = 1k , c l = 3.7pf - 100 - s t recover output overload recovery time, recovery to 90% of output saturation a v = +2, r f = 10k , r l = 100k, c l = 3.7pf - 3.1 - s v os input offset voltage -2.5 -0.2 2.5 v t a = -40c to +85c -3.4 - 3.4 v t a = -40c to +125c -4 - -4 v tcv os input offset voltage temperature coefficient t a = -40c to +125c -15 -0.5 15 nv/c electrical specifications v s = 5v, v cm = 2.5v, t a = +25c, unless otherwise specified . boldface limits apply across the specified operating temperature range. (continued) parameter description test conditions min ( note 8 )typ max ( note 8 )units
isl28134 fn6957 rev 6.00 page 6 of 25 october 14, 2014 electrical specifications v s = 2.5v, v cm = 1.25v, t a = +25c, unless otherwise specified. boldface limits apply over the specified operating temperature range. parameter description test conditions min ( note 8 )typ max ( note 8 )units dc specifications i b input bias current -300 120 300 pa t a = -40c to +85c -300 - 300 pa t a = -40c to +125c -550 - 550 pa tci b input bias current temperature coefficient t a = -40c to +85c - 1.4 - pa/c t a = -40c to +125c - 2 - pa/c i os input offset current -600 240 600 pa t a = -40c to +85c -600 - 600 pa t a = -40c to +125c -750 - 750 pa tci os input offset current temperature coefficient t a = -40c to +85c - 2.8 - pa/c t a = -40c to +125c - 4 - pa/c common mode input voltage range v+ = 2.5v, v- = 0v guaranteed by cmrr -0.1 - 2.6 v cmrr common mode rejection ratio v cm = -0.1v to 2.6v 120 135 - db v cm = -0.1v to 2.6v 115 --db i s supply current per amplifier r l = open - 715 940 a r l = open t a = -40c to +85c - - 1115 a r l = open t a = -40c to +125c - - 1190 a i sc short circuit output source current r l = short to ground - 65 - ma short circuit output sink current r l = short to v+ - -65 - ma v oh output voltage swing, high from v out to v + r l = 10k to v cm 15 10 - mv r l = 10k to v cm 15 --mv v ol output voltage swing, low from v - to v out r l = 10k to v cm - 10 15 mv r l = 10k to v cm -- 15 mv ac specifications c in input capacitance differential - 5.2 - pf common mode - 5.6 - pf e n input noise voltage f = 0.1hz to 10hz - 250 400 nv p-p f = 10hz - 8 - nv/ ? hz f = 1khz - 10 - nv/ ? hz i n input noise current f = 1khz - 200 - fa/ ? hz gbwp gain bandwidth product - 3.5 - mhz
isl28134 fn6957 rev 6.00 page 7 of 25 october 14, 2014 transient response sr positive slew rate v+ = 2.5v, v- = 0v, v out = 0.25v to 2.25v, r l = 100k , c l =3.7pf -1.5- v/s negative slew rate - 1.0 - v/s t r , t f , small signal rise time, t r 10% to 90% v+ = 2.5v, v- = 0v, v out = 0.1v p-p , r f = 0 , r l = 100k , c l =3.7pf -0.07- s fall time, t f 10% to 90% - 0.17 - s t r , t f large signal rise time, t r 10% to 90% v+ = 2.5v, v- = 0v, v out = 2v p-p , r f =0 , r l = 100k , c l =3.7pf -1.3- s fall time, t f 10% to 90% - 2.0 - s t s settling time to 0.1%, 2v p-p step a v = -1, r f = 1k , c l = 3.7pf - 100 - s t recover output overload recovery time, recovery to 90% of output saturation a v = +2, r f = 10k , r l = 100k, c l = 3.7pf -1.5- s note: 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications v s = 2.5v, v cm = 1.25v, t a = +25c, unless otherwise specified. boldface limits apply over the specified operating temperature range. (continued) parameter description test conditions min ( note 8 )typ max ( note 8 )units typical performance curves t a = +25c, v cm = 0v unless otherwise specified. figure 3. v os vs temperature, v s = 2.5v figure 4. v os vs temperature, v s = 1.125v figure 5. v os histogram v s = 5v figure 6. tcv os histogram v s = 5v offset voltage (v) temperature (c) -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 v s = 2.5v v cm = 0v -50 -20 10 40 70 100 130 -50 -20 10 40 70 100 130 offset voltage (v) temperature (c) -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 v s = 1.125v v cm = 0v number of amplifiers -2.0 -1.5 -1.0 -0.5 -2.5 0 200 400 600 800 1000 1200 0 0.5 1.0 1.5 2.0 2.5 1400 v os (v) v s = 2.5v n = 2796 v cm = 0v t = -40c to +125c 1600 tcv os (nv/c) number of amplifiers -8 -6 -4 -2 -10 0 20 40 60 80 100 120 0246810 v s = 2.5v n = 480 v cm = 0v t = -40c to +125c 140 160
isl28134 fn6957 rev 6.00 page 8 of 25 october 14, 2014 figure 7. v os histogram v s = 2.5v figure 8. tcv os histogram v s = 2.5v figure 9. v os vs v cm figure 10. v os vs supply voltage figure 11. i b vs v cm figure 12. i os vs v cm typical performance curves t a = +25c, v cm = 0v unless otherwise specified. (continued) number of amplifiers -2.0 -1.5 -1.0 -0.5 -2.5 0 200 400 600 800 1000 1200 0 0.5 1.0 1.5 2.0 2.5 1400 v os (v) v s = 1.25v n = 2325 v cm = 0v t = -40c to +125c tcv os (nv/c) number of amplifiers -8 -6 -4 -2 -10 0 20 40 60 80 100 120 02 46810 v s = 1.25v n = 310 v cm = 0v t = -40c to +125c common mode voltage (v) offset voltage (v) -2.4 -1.6 -0.8 0 -3.2 0.8 1.6 2.4 3.2 -4 -3 -2 -1 0 1 2 3 4 v s = 2.5v v s = 1.125v offset voltage (v) supply voltage (v) -4 -3 -2 -1 0 1 2 3 4 1.5 2.0 2.5 3.0 1.0 3.5 common mode voltage (v) input bias current (pa) -2 -1 0 -3 123 -200 -100 0.00 100 200 300 400 500 -400 -300 -500 i b- v s = 2.5v i b- v s = 1.125v i b+ v s = 1.125v i b+ v s = 2.5v common mode voltage (v) input offset current (pa) -2 -1 0 -3 12 3 v s = 2.5v v s = 1.125v -200 -100 100 200 300 400 500 600
isl28134 fn6957 rev 6.00 page 9 of 25 october 14, 2014 figure 13. i b vs temperature figure 14. i os vs temperature figure 15. cmrr and psrr vs temperature fig ure 16. supply current vs supply voltage figure 17. output high overhead voltage vs load current figure 18. output low overhead voltage vs load current typical performance curves t a = +25c, v cm = 0v unless otherwise specified. (continued) input bias current (pa) temperature (c) v s = 2.5v i b+ v s = 1.125v i b- v s = 2.5v i b- v s = 1.125v i b+ -20 0 80 60 -40 -50 0 50 100 150 200 250 300 350 -100 20 40 100 120 140 input offset current (pa) temperature (c) v s = 2.5v v s = 1.125v -20 0 80 60 -40 20 40 100 120 140 -50 0 50 100 150 200 250 300 350 -100 -150 temperature (c) cmrr/psrr (db) 100 110 120 130 140 150 160 v cm = 0v v s = 1.125v to 3v psrr v cm = -2.6v to +2.6v v s =2.5v cmrr psrr -20 0 80 60 -40 20 40 100 120 140 cmrr supply current (a) supply voltage (v) 500 600 700 800 900 1000 2.0 3.0 4.0 5.0 6.0 t = +125c t = +25c t = +85c t = -40c load current (ma) voltage from v+ rail (mv) 1 10 100 1000 v s = 2.5v t = -40c to +125c 0.01 0.1 1.0 10 100 load current (ma) voltage from v- rail (mv) 1 10 100 1000 0.01 0.1 1.0 10 v s = 2.5v t = -40c to +125c 100
isl28134 fn6957 rev 6.00 page 10 of 25 october 14, 2014 figure 19. v oh vs temperature figure 20. v ol vs temperature figure 21. input noise voltage density vs frequency figure 22. input noise voltage 0.1hz to 10hz figure 23. input noise current density vs freque ncy figure 24. open loop gain and phase, r l = 10m typical performance curves t a = +25c, v cm = 0v unless otherwise specified. (continued) temperature (c) voltage from v+ rail (mv) r l = 12.5k v s = 2.5v r l = out to gnd r l = 1k -20 0 80 60 -40 20 40 100 120 140 0.001 0.01 0.1 1.0 temperature (c) voltage from v- rail (mv) v s = 2.5v r l = out to gnd r l = 1k r l = 12.5k 0.001 0.01 0.1 1.0 -20 0 80 60 -40 20 40 100 120 140 1 10 100 0.001 0.01 0.1 1 10 frequency (hz) noise (nvhz) voltage (nv) time (s) 110 23456789 0 -300 -200 -100 0.00 100 200 300 v s = 2.5v a v = 10,000 r g = 10, r f = 100k 0.1 1 10 100 1000 10k 100k current noise (fa/hz) frequency (hz) 100 1000 v s = 2.5v a v = 1 r s = 5m 10 ci n+ =100pf c in+ = 0pf gain (db) / phase () 0 20 40 60 80 100 120 140 -20 v s = 2.5v simulation r l = 10m gain phase 0.1 1 10 100 1k 10k 1m frequency (hz) 100k 10m 100m
isl28134 fn6957 rev 6.00 page 11 of 25 october 14, 2014 figure 25. open loop gain and phase, r l = 10k figure 26. frequency response vs closed loop gain figure 27. gain vs frequency vs r l, v s = 2.5v figure 28. gain vs frequency vs r l, v s = 5.0v figure 29. gain vs frequency vs feedback resistor values r f /r g figure 30. gain vs frequency vs v out typical performance curves t a = +25c, v cm = 0v unless otherwise specified. (continued) gain (db) / phase () 0 20 40 60 80 100 120 140 -20 v s = 2.5v simulation r l = 10k gain phase 0.1 1 10 100 1k 10k 1m frequency (hz) 100k 10m 100m 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 100m frequency (hz) gain (db) 10m 80 90 -10 -20 -30 -40 a v = 1000 a v = 10,000 a v = 100 a v = 10 a v = 1 r g = open, r f = 0 r g = 10k, r f = 100k r g = 1k, r f = 100k r g = 100, r f = 100k r g = 10, r f = 100k v s = 2.5v v out = 10mv p-p c l = 3.7pf r l = 100k gain (db) frequency (hz) 10k 100k 1m 10m v s = 1.25v v out = 10mv p-p a v = 1v c l = 3.7pf r l > 10k r l = 1k -6 -4 -2 0 2 -8 -5 -3 1 1 -7 -6 -4 -2 0 2 4 -8 -10 gain (db) frequency (hz) 100k 1m 10m 100m v s = 2.5v v out = 10mv p-p a v = 1v c l = 3.7pf r l = 1k r l > 10k normalized gain (db) -10 -5 0 5 10 15 100 1k 10k 100k 1m 100m frequency (hz) 10m v s = 2.5v v out = 10mv p-p a v = 2v r l = 100k r g = 100k, r f = 100k r g = 10k, r f = 10k r g = 1k, r f = 1k 10 100 1k 10k 100k 1m 100m 10m gain (db) frequency (hz) -6 -4 -2 0 2 -8 -10 v s = 2.5v c l = 3.7pf a v = 1v r l = open 1v p-p 500mv p-p 250mv p-p 100mv p-p 10mv p-p
isl28134 fn6957 rev 6.00 page 12 of 25 october 14, 2014 figure 31. gain vs frequency vs c l figure 32. gain vs frequency vs supply voltage figure 33. emirr at in+ pin vs frequency figure 34. cmrr vs frequency, v s = 5v figure 35. cmrr vs frequency, v s = 2.5v typical performance curves t a = +25c, v cm = 0v unless otherwise specified. (continued) frequency (hz) gain (db) -6 -4 -2 0 2 4 6 8 10 12 10k 100k 1m 100m 10m v s = 2.5v v out = 10mv p-p a v = 1v r l = 100k 824pf 1nf 474pf 104pf 51pf 3.7pf frequency (hz) gain (db) -6 -4 -2 0 2 -8 -10 1m 10m 0.8v 3.0v c l = 3.7pf a v = 1v r l = 100k v out = 10mv p-p 1.5v 0 20 40 60 80 100 120 10 100 1k 10k emirr in+ (db) frequency (mhz) cmrr (db) frequency (hz) 1m 0.1 10 1k 40 60 80 100 120 140 20 v s = 2.5v simulation v cm = 0v 100k 10m 160 cmrr (db) frequency (hz) 1m 0.1 10 1k 40 60 80 100 120 140 20 v s = 1.25v simulation v cm = 0v 100k 10m 160
isl28134 fn6957 rev 6.00 page 13 of 25 october 14, 2014 figure 36. psrr vs frequency, v s = 5v figure 37. psrr vs frequency, v s = 2.5v figure 38. no phase inversion figure 39. large signal step response (3v) figure 40. large signal step response (1v) figure 41. small signal step response (100mv) typical performance curves t a = +25c, v cm = 0v unless otherwise specified. (continued) frequency (hz) gain (db) 10 100 1k 10k 100k 1m 10m 120 100 80 60 40 20 0 140 +psrr v s = 2.5v dc v in = 1v p-p a v = 1v r l = 100k -psrr frequency (hz) gain (db) 10 100 1k 10k 100k 1m 10m 120 100 80 60 40 20 0 v s = 1.25v dc v in = 1v p-p a v = 1v r l = 100k -psrr +psrr time (ms) 0 5 10 15 20 -4 -3 -2 -1 0 1 2 3 4 voltage (v) v s = 2.5v v in = -3v to 3v a v = 1v r l = 1m time (s) voltage (v) 0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v s = 5v dc v in = 1v to 4v a v = 1v r l = 100k input output time (s) voltage (v) 0246810 0 0.2 0.4 0.6 0.8 1.0 1.2 v s = 5v dc v in = 0.1v to 1.1v a v = 1v r l = 100k input output time (s) voltage (v) 0246810 -0.04 0.02 0.04 0.06 0.08 0.10 v s = 2.5v dc v in = 0v to 0.1v a v = 1v r l = 100k 0 -0.02 output input
isl28134 fn6957 rev 6.00 page 14 of 25 october 14, 2014 applications information functional description the isl28134 is a single 5v rail-to-rail input/output amplifier that operates on a single or dual supply. the isl28134 uses a proprietary chopper-stabilized technique that combines a 3.5mhz main amplifier with a very high open loop gain (174db) chopper amplifier to achieve very low offset voltage and drift (0.2v, 0.5nv/c) while having a low supply current (675a). the very low 1/f noise corner <0.1hz and low input noise voltage (8nv/ hz at 100hz) of the amplifier makes it ideal for low frequency precision applications requiring very high gain and low noise. this multi-path amplifier architec ture contains a time continuous main amplifier whose input dc offset is corrected by a parallel-connected, high gain chopper stabilized dc correction amplifier operating at 100khz. from dc to ~10khz, both amplifiers are active with the dc offset correction active with most of the low frequency gain provided by the chopper amplifier. a 10khz crossover filter cuts off the low frequency chopper amplifier path leaving the main amplifier active out to the -3db frequency (3.5mhz gbwp). the key benefits of this architecture for precision applications are rail-to-rail inputs/outputs, high open loop gain, low dc offset and temperature drift, low 1/f noise corner and low input noise voltage. the noise is virtually flat across the frequency range from a few mhz out to 100khz, except for the narrow noise peak at the amplifier crosso ver frequency (10khz). power supply considerations the isl28134 features a wide supply voltage operating range. the isl28134 operates on single (+2.25v to +6.0v) or dual (1.125 to 3.0v) supplies. power supply voltages greater than the +6.5v absolute maximum (specified in the ? absolute maximum ratings ? on page 4 ) can permanently damage the device. performance of the device is optimized for supply voltages greater than 2.5v. this makes the isl28134 ideal for portable 3v battery applications that require the precision performance. it is highly recommended that a 0.01f or larger high frequency decoupling capacitor is placed across the power supply pins of the ic to maintain high performance of the amplifier. rail-to-rail input and output (rrio) unlike some amplifiers whose inputs may not be taken to the power supply rails or whose outputs may not drive to the supply rails, the isl28134 features rail-to-rail inpu ts and outputs. this allows the amplifier inputs to have a wide common mode range (100mv beyond supply rails) while main taining high cmrr (135db) and maximizes the signal to noise rati o of the amplifier by having the v oh and v ol levels be at the v+ and v- rails, respectively. low input voltage noise performance in precision applications, the input noise of the front end amplifier is a critical parameter. combined with a high dc gain to amplify the small input signal, the input noise voltage will result in an output error in the amplifier. a 1v p-p input noise voltage with an amplifier gain of 10,000v/v will result in an output offset in the range of 10mv, which can be an unacceptable error source. with only 250nv p-p at the input, along with a flat noise response down to 0.1hz, the isl28134 can amplify small input signals with minimal output error. the isl28134 has the lowest input noise voltage compared to other competitor zero drift amplifiers with similar supply currents (see table 1 ). the overall input referred voltage noise of an amplifier can be expressed as a sum of the input noise voltage, input noise current of the amplifier and the johnson noise of the gain-setting resistors used. the product of the input noise current and external feedback resistors along with the johnson noise, increases the tota l output voltage noise as the value of the resistance goes up. for optimizing noise performance, choose lower value feedback resistors to minimize the effect of input noise current. although the isl28134 features a very low 200fa/ ? hz input noise current, at source impedances >100k , the input referred noise voltage will be dominated by the input current noise. keep source input impedances under 10k for optimum performance. figure 42. small signal overshoot vs load capacitance, vs = 2.5v figure 43. small signal oversh oot vs load capacitance, v s = 1.25v typical performance curves t a = +25c, v cm = 0v unless otherwise specified. (continued) load capacitance (pf) overshoot (%) 10 100 1000 10 15 20 25 30 35 40 45 50 55 60 - os +os v s = 2.5v v out = 100mv p-p a v = 1v r l = 100k load capacitance (pf) overshoot (%) 10 100 1000 10 15 20 25 30 35 40 45 50 55 v s = 1.25v v out = 100mv p-p a v = 1v r l = 100k - os +os
isl28134 fn6957 rev 6.00 page 15 of 25 october 14, 2014 high source impedance applications the input stage of chopper stabilized amplifiers do not behave like conventional amplifier input stages. the isl28134 uses switches at the chopper amplifie r input that continually ?chops? the input signal at 100khz to reduce input offset voltage down to 1v. the dynamic behavior of these switches induces a charge injection current to the input terminals of the amplifier. the charge injection current has a dc path to ground through the resistances seen at the input term inals of the amplifier. higher input impedance cause an apparent shift in the input bias current of the amplifier. inpu t impedances larger than 10k begin to have significant incr eases in the bias currents. to minimize the effect of impedance on input bias currents, an input resistance of <10k is recommended. because the chopper amplifier has charge injection currents at each terminal, the input impedance should be balanced across each input (see figure 44 ). the input impedance of the amplifier should be matched between the in+ and in- terminals to minimize total input offset curren t. input offset currents show up as an additional output offset voltage, as shown in equation 1 : if the offset voltage of the amplifier is negative, the input offset currents will add to the total output offset. for a 10,000v/v gain amplifier using 1m feedback resistor, a 500pa total input offset current will have an additional outp ut offset voltage of 0.5mv. by keeping the input impedance low and balanced across the amplifier inputs, the input offset current is kept below 100pa, resulting in an offset voltage 0.1mv or less. in+ and in- protection the isl28134 is capable of driving the input terminals up to and beyond the supply rails by about 0.5v. back biased esd diodes from the input pins to the v+ an d v- rails will conduct current when the input signals go more than 0.5v beyond the rail (see figure 45 ). the esd protection diodes must be current limited to 20ma or less to prevent damage of the ic. this current can be reduced by placing a resistor in se ries with the in+ and in- inputs in the event the input signals go beyond the rail. emi rejection electromagnetic interference (emi) can be a problem in high frequency applications for precision amplifiers. the op amp pins are susceptible to emi signals wh ich can rectify high frequency inputs beyond the amplifier bandwidth and present itself as a shift in dc offset voltage. long trace leads to op amp pins may act as an antenna for radiated rf signals, which result in a total conductive emi noise into the op amp inputs. the most susceptible pin is the non-inverting in+ input therefore, emi rejection (emir) on this pin is important for rf type applications. the ability of the am plifier output to reject emi is called emi rejection ratio (emirr) and is computed as: emirr (db) = 20 log (v in_peak / v os the test circuit for measuring the dc offset of the amplifier with an rf signal input to the in+ pin is shown in figure 46 . the emirr performance of the isl28134 at the in+ pin across a frequency of 10mhz to 2.4ghz is plotted on figure 33 . the isl28134 shows a typical emirr of 75db at 1ghz. for better emi immunity, a small rfi filter ca n be placed at the input to attenuate out of band signals an d reduce dc offset shift from high frequency rf signals into the in+ pin. for example, a 15 and 100pf rc filter will roll off signals above 100mhz for better emirr performance. table 1. part voltage noise at 100hz 0.1hz to 10hz peak-to-peak voltage noise competitor a 22nv/ hz 600nv p-p competitor b 16nv/ hz 260nv p-p competitor c 90nv/ hz 1500nv p-p isl28134 8nv/ hz 250nv p-p v ostot = v os - r f *i os (eq. 1) figure 44. circuit implementation for reducing input bias currents - + r f r i r s +2.5v -2.5v v out r l r g r f //r i = r s //r g v in figure 45. input current limiting - + r in r l v in v out v+ v- esd diodes in- in+ figure 46. circuit testing emirr - + r l = 10k v in = 200mv p-p v out in- in+ -2.5v +2.5v
isl28134 fn6957 rev 6.00 page 16 of 25 october 14, 2014 output phase reversal the output phase reversal is the unexpected inversion of the amplifier output signal when the inputs exceed the common mode input range. since the isl28134 is a rail-to-rail input amplifier, the isl28134 is specifically designed to prevent output phase reversal within its common mode input range. in fact, the isl28134 will not phase invert even when the input signals go 0.5v beyond the supply rails (see figure 38 ). if input signals are expected to go beyond the rails, it is highly recommended to minimize the forward biased esd diode current to prevent phase inversion by placing a resistor in series with the input. high gain, precision dc-coupled amplifier precision applications that need to amplify signals in the range of a few v require gain in the order of thousands of v/v to get a good signal to the analog to digital converter (adc). this can be achieved by using a very high ga in amplifier with the appropriate open loop gain and bandwidth. in addition to the high gain and bandwidth, it is important that the amplifier have low v os and temperature drift along with a low input noise voltage. for example, an amplifier with 100v offset voltage and 0.5v/c offset drift configured in a closed loop gain of 10,000v/v would produce an output error of 1v and a 5mv/c temperature dependent erro r. unless offset trimming and temperature compensation techniques are used, this error makes it difficult to resolve the input voltages needed in the precision application. the isl28134 features a low v os of 4v max and a very stable 10nv/ c max temperature drift, which produces an output error of only 40mv and a temperature erro r of 0.1mv/c. with an ultra low input noise of 210nv p-p (0.1hz to 10hz) and no 1/f corner frequency, the isl28134 is capable of amplifying signals in the v range with high accuracy. for even further dc precision, some feedback filtering c f (see figure 47 ) to reduce the noise can be implemented as a total signal stage amplifier. as a method of best practice, the isl28134 should be impedance matched at the two input terminals. a balancing capacitor of the same value at the on-inverting terminal will result in the amplifier input impedances tracking across frequency isl28134 spice model figure 48 shows the spice model schematic and figure 49 shows the net list for the spice model. the model is a simplified version of the actual device and simulates important ac and dc parameters. the ac parameters in corporated into the model are: 1/f and flat band noise voltage, slew rate, cmrr, and gain and phase. the dc parameters are i os , v os , total supply current, output voltage swing and output current limit (65ma). the model uses typical parameters given in the ?electrical specifications? table beginning on page 4 . the avol is adjusted for 174db with the dominant pole at 6.5mhz. the cmrr is set at 135db, f = 200hz. the input stage models th e actual device to present an accurate ac representation. th e model is configured for an ambient temperature of +25c. figures 50 through 63 show the characteriza tion vs simulation results for the noise voltage, open loop gain phase, closed loop gain vs frequency, cmrr, large signal 3v step response, large signal 1v step response, and output voltage swing v oh /v ol 2.5v supplies (no phase inversion). license statement the information in the spice model is protected under united states copyright laws. intersil corporation hereby grants users of this macro-model, hereto referred to as ?licensee?, a nonexclusive, nontransferable license to use this model, as long as the licensee abides by the terms of this agreement. before using this macro-model, the licens ee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. the licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro-model to suit his/her sp ecific applications, and the licensee may make copies of this macro-model for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including but not limited to any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connectio n with or arising out of the use of this macro-model. inters il reserves the right to make changes to the product and the macro-model without prior notice. figure 47. high gain, precision dc-coupled amplifier - + 100 r l v in v out 1m 1m -2.5v +2.5v a cl = 10kv/v c f 100 c f
fn6957 rev 6.00 page 17 of 25 october 14, 2014 isl28134 figure 48. spice schematic in- in+ common mode gain stage with zero output stage 2nd pole stage input stage 1st gain stage mid supply ref v supply isolation stage 2nd gain stage differential to single ended conversion stage voltage noise stage 7 4 12 13 2 vin- 6 en vcm vin+ 1 29 19 20 17 26 vmid 5 28 18 22 v-- vc 23 21 10 24 25 vout 27 3 8 11 9 vg 15 14 16 v- v++ v+ 0 0 0 0 dx d3 dx d3 r15 1.00e-03 r15 1.00e-03 r17 1136.85 r17 1136.85 dx d10 dx d10 r4 10 r4 10 dx d9 dx d9 dx d4 dx d4 r19 50 r19 50 ra2 1 ra2 1 r14 7346.06e6 r14 7346.06e6 m15 nchannelmosfet m15 nchannelmosfet v2 1e-6 v2 1e-6 cindif 4.71e-12 cindif 4.71e-12 + - g3 gain = 68.225e-3 + - g3 gain = 68.225e-3 c5 10e-12 c5 10e-12 - + + - en - + + - en + - g2a gain = 233.426 + - g2a gain = 233.426 r8 7.5 r8 7.5 + - g7 gain = 879.62e-6 + - g7 gain = 879.62e-6 r5 10 r5 10 r22 5e11 r22 5e11 r16 1.00e-03 r16 1.00e-03 r23 5e11 r23 5e11 + - g5 gain = 177.83e-6 + - g5 gain = 177.83e-6 r6 10 r6 10 i1 5e-3 i1 5e-3 - + + - e3 gain = 1 - + + - e3 gain = 1 v4 0.607 v4 0.607 v5 0.607 v5 0.607 r21 80 r21 80 r10 1e9 r10 1e9 m14 nchannelmosfet m14 nchannelmosfet r7 7.5 r7 7.5 i2 5e-3 i2 5e-3 r3 10 r3 10 v1 1e-6 v1 1e-6 cin2 10.1e-12 cin2 10.1e-12 v8 1.04 v8 1.04 v7 1.04 v7 1.04 l1 7.957e-07 l1 7.957e-07 m10 pmosisil m10 pmosisil - + + - eos - + + - eos dy d11 dy d11 v9 0.14 v9 0. r2 7.5004 r2 7.5004 + - g6 gain = 177.83e-6 + - g6 gain = 177.83e-6 r18 1136.85 r18 1136.85 r9 100 r9 100 - + + - e2 gain = 1 - + + - e2 gain = 1 vos 0.2e-6 vos 0.2e-6 v6 0.607 v6 0.607 r12 1 r12 1 + - g4 gain = 68.225e-3 + - g4 gain = 68.225e-3 cin1 10.1e-12 cin1 10.1e-12 dx d8 dx d8 c2 3.33e-09 c2 3.33e-09 + - g11 gain = 20e-3 + - g11 gain = 20e-3 + - g12 gain = 20e-3 + - g12 gain = 20e-3 + - g1a gain = 233.426 + - g1a gain = 233.426 - + + - e4 - + + - e4 isy 675e-6 isy 675e-6 + - g8 gain = 879.62e-6 + - g8 gain = 879.62e-6 dx d6 dx d6 dx d5 dx d5 r1 7.5004 r1 7.5004 ra1 1 ra1 1 dx d2 dx d2 r11 1 r11 1 c4 10e-12 c4 10e-12 dn d13 dn d13 dy d12 dy d12 v3 0.607 v3 0.607 dx d1 dx d1 dx d7 dx d7 c3 3.33e-09 c3 3.33e-09 r13 7346.06e6 r13 7346.06e6 r20 50 r20 50 + - g2 gain = 113.96e-3 + - g2 gain = 113.96e-3 + - g9 gain = 20e-3 + - g9 gain = 20e-3 l2 7.957e-07 l2 7.957e-07 ios 240e-12 ios 240e-12 + - g1 gain = 113.96e-3 + - g1 gain = 113.96e-3 + - g10 gain = 20e-3 + - g10 gain = 20e-3 m11 pmosisil m11 pmosisil
isl28134 fn6957 rev 6.00 page 18 of 25 october 14, 2014 *isl28134 macromodel * *revision history: * revision a, lafontaine june 17th 2011 * model for noise, quiescent supply currents, *cmrr135db f = 200hz, avol 174db f = *6.5mhz, sr = 1.5v/us, gbwp 3.5mhz. *copyright 2011 by intersil corporation *refer to data sheet license statement *use of this model indicates your acceptance *with the terms and provisions in the license *statement. * *intended use: *this pspice macromodel is intended to give *typical dc and ac performance *characteristics under a wide range of *external circuit configurations using *compatible simulation platforms C such as *isim pe. * *device performance features supported by *this model: *typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *open and closed loop i/o impedances, *open loop gain and phase, *closed loop bandwidth and frequency *response, *loading effects on closed loop frequency *response, *input noise terms including 1/f effects, *slew rate, input and output headroom limits *to i/o voltage swing, supply current at *nominal specified supply voltages, *output current limiting (65ma) * *device performance features not *supported by this model: *harmonic distortion effects, *disable operation (if any), *thermal effects and/or over temperature *parameter variation, *performance variation vs. supply voltage, *part to part performance variation due to *normal process parameter spread, *any performance difference arising from *different packaging, *load current reflected into the power supply *current. * source isl28134 * * connections: +input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28134 vin+ vin- v+ v- vout * *voltage noise e_en vin+ en 28 0 1 d_d13 29 28 dn v_v9 29 0 0.14 r_r21 28 0 80 * *input stage m_m10 11 vin- 9 9 pmosisil m_m11 12 1 10 10 pmosisil m_m14 3 1 5 5 nchannelmosfet m_m15 4 vin- 6 6 nchannelmosfet i_i1 7 v-- dc 5e-3 i_i2 v++ 8 dc 5e-3 i_ios vin- 1 dc 240e-12 g_g1a v++ 14 4 3 233.4267 g_g2a v-- 14 11 12 233.4267 v_v1 v++ 2 1e-6 v_v2 13 v-- 1e-6 v_vos en 30 0.2e-6 r_r1 3 2 7.5004 r_r2 4 2 7.5004 r_r3 5 7 10 r_r4 7 6 10 r_r5 9 8 10 r_r6 8 10 10 r_r7 13 11 7.5 r_r8 13 12 7.5 r_ra1 14 v++ 1 r_ra2 v-- 14 1 c_cindif vin- en 4.71e-12 c_cin1 v-- 30 10.1e-12 c_cin2 v-- vin- 10.1e-12 * *1st gain stage g_g1 v++ 16 15 vmid 113.96e-3 g_g2 v-- 16 15 vmid 113.96e-3 v_v3 17 16 0.607 v_v4 16 18 0.607 d_d1 15 vmid dx d_d2 vmid 15 dx d_d3 17 v++ dx d_d4 v-- 18 dx r_r9 15 14 100 r_r10 15 vmid 1e9 r_r11 16 v++ 1 r_r12 v-- 16 1 * *2nd gain stage g_g3 v++ vg 16 vmid 68.225e-3 g_g4 v-- vg 16 vmid 68.225e-3 v_v5 19 vg 0.607 v_v6 vg 20 0.607 d_d5 19 v++ dx d_d6 v-- 20 dx r_r13 vg v++ 7346.06e6 r_r14 v-- vg 7346.06e6 c_c2 vg v++ 3.33e-09 c_c3 v-- vg 3.33e-09 * *mid supply ref e_e4 vmid v-- v++ v-- 0.5 * *supply isolation stage e_e2 v++ 0 v+ 0 1 e_e3 v-- 0 v- 0 1 i_isy v+ v- dc 675e-6 * *common mode gain stage g_g5 v++ vc vcm vmid 177.83e-6 g_g6 v-- vc vcm vmid 177.83e-6 e_eos 1 30 vc vmid 1 r_r15 vc 21 1.00e-03 r_r16 22 vc 1.00e-03 r_r22 en vcm 5e11 r_r23 vcm vin- 5e11 l_l1 21 v++ 7.957e-07 l_l2 22 v-- 7.957e-07 * *2nd pole stage g_g7 v++ 23 vg vmid 879.62e-6 g_g8 v-- 23 vg vmid 879.62e-6 r_r17 23 v++ 1136.85 r_r18 v-- 23 1136.85 c_c4 23 v++ 10e-12 c_c5 v-- 23 10e-12 * *output stage g_g9 26 v-- vout 23 20e-3 g_g10 27 v-- 23 vout 20e-3 g_g11 vout v++ v++ 23 20e-3 g_g12 v-- vout 23 v-- 20e-3 v_v7 24 vout 1.04 v_v8 vout 25 1.04 d_d7 23 24 dx d_d8 25 23 dx d_d9 v++ 26 dx d_d10 v++ 27 dx d_d11 v-- 26 dy d_d12 v-- 27 dy r_r19 vout v++ 50 r_r20 v-- vout 50 * .model pmosisil pmos (kp=16e-3 vto=-0.6 +kf=0 af=1) .model nchannelmosfet nmos (kp=3e-3 +vto=0.6 kf=0 af=1) .model dn d(kf=6.69e-9 af=1) .model dx d(is=1e-12 rs=0.1 kf=0 af=1) .model dy d(is=1e-15 bv=50 rs=1 kf=0 +af=1) .ends isl28134 figure 49. spice net list
isl28134 fn6957 rev 6.00 page 19 of 25 october 14, 2014 characterization vs simulation results figure 50. characterized input noise voltage figure 51. simulated input noise voltage figure 52. characterized open-loop gain, phase vs frequency figure 53. simulated open-loop gain, phase vs frequency figure 54. characterized closed-loop gain vs freque ncy figure 55. simulated closed-loop gain vs frequency voltage noise (nv/hz) frequency (hz) 0.1 1 10 100 1000 10k 100k 1 10 100 v s = 2.5v a v = 1 0.01 0.001 1.0m 10m 100m 1.0 10 100 1.0k 10k 100k 1.0 10 100 400 voltage noise (nv/hz) frequency (hz) v s = 2.5v a v = 1 0.1 1 10 100 1k 10k 1m frequency (hz) gain (db) / phase () 100k 10m 0 20 40 60 80 100 120 140 -20 v s = 2.5v simulation r l = 10m gain phase 100m gain (db) / phase () 0 20 40 60 80 100 120 140 -20 0.1 1 10 100 1k 10k 1m frequency (hz) 100k 10m 100m v os = 0 gain phase 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 100m frequency (hz) gain (db) 10m 80 90 -10 -20 -30 -40 a v = 1000 a v = 10,000 a v = 100 a v = 10 a v = 1 r g = open, r f = 0 r g = 10k, r f = 100k r g = 1k, r f = 100k r g = 100, r f = 100k r g = 10, r f = 100k v s = 2.5v v out = 10mv p-p c l = 3.7pf r l = 100k 0 10 20 30 40 50 60 70 10 100 1k 10k 100k 1m 100m frequency (hz) gain (db) 10m 80 90 -10 -20 -30 -40 a v = 1000 a v = 10,000 a v = 100 a v = 10 a v = 1 r g = 10k, r f = 100k r g = 1k, r f = 100k r g = 100, r f = 100k r g = 10, r f = 100k v s = 2.5v v out = 10mv p-p c l = 3.7pf r l = 100k r g = open, r f = 0
isl28134 fn6957 rev 6.00 page 20 of 25 october 14, 2014 figure 56. characterized cmrr vs frequency f igure 57. simulated cmrr vs frequency figure 58. characterized large signal step response (3v) figure 59. simulated large signal step response (3v) figure 60. characterized smal l-signal transient response figure 61. simulated small-signal transient response characterization vs simulation results (continued) cmrr (db) frequency (hz) 1m 0.1 10 1k 40 60 80 100 120 140 20 v s = 2.5v simulation v cm = 0v 100k 10m 160 cmrr (db) frequency (hz) 1m 0.1 10 1k 40 60 80 100 120 140 20 v s = 2.5v simulation v cm = 0v 100k 10m 160 time (s) voltage (v) 0 2 4 6 8 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v s = 5v dc v in = 1v to 4v a v = 1v r l = 100k input output time (s) voltage (v) 0 2 4 6 8 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v s = 5v dc v in = 1v to 4v a v = 1v r l = 100k input output time (s) voltage (v) 0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1.0 1.2 v s = 5v dc v in = 0.1v to 1.1v a v = 1v r l = 100k input output time (s) voltage (v) 0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1.0 1.2 v s = 5v dc v in = 0.1v to 1.1v a v = 1v r l = 100k input output
isl28134 fn6957 rev 6.00 page 21 of 25 october 14, 2014 figure 62. characterized no phase inversion figure 63. simulated no phase inversion, v oh and v ol characterization vs simulation results (continued) time (ms) 0 5 10 15 20 -4 -3 -2 -1 0 1 2 3 4 voltage (v) v s = 2.5v v in = -3v to 3v a v = 1v r l = 1m 0 0.2 0.4 0.6 0.8 1.0 -4.0 -2.0 0 2.0 4.0 v s = 2.5v v in = -4v to 4v a v = 1v r l = 1m time (ms) voltage (v) v oh = 2.489v v ol = -2.489v
isl28134 fn6957 rev 6.00 page 22 of 25 october 14, 2014 revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change october 14, 2014 fn6957.6 figure 44 updated from: r s //r g = r s //r g to: r f //r i = r s //r g. removed part numbers isl28134fruz-t7 and is l28134fbz from ordering information table. removed 6 ld utdfn throughout the document. removed pod l6.1.6x1.6. july 3, 2013 fn6957.5 updated the figure 1 on page 1, and change d title from ?precision 10-bit weigh scale/strain gauge? to ?precision weigh scal e / strain gauge?. updated figure 21: ?input noise voltage density vs frequency? on page 10. added typical emirr spec to electrical spec ta ble under section ?ac specifications? on page 5. added applications paragraph to ?emi rejection? on page 15. added 2 figures, 33 and 46, describing the test circui t and typical performance graph for ?emi rejection? on page 15. august 3, 2012 fn6957.4 made correction to figure 1 on page 1 by changing resistor label from ?1m ? ? to ?20k ? ?. december 12, 2011 fn6957.3 updated front page introducti on to reflect +125c grade and sot-23 package release. updated figure 1 with newer relevant apps circuit updated figure 2 with extended temp range -40c to 125c updated ?ordering information? on page 3 by removing ?coming soon? from isl28134fhz sot-23 packages. updated ?operating conditions? on page 4 to include full industrial grade package. updated ?electrical specifications? tables for both vs = 5v and vs = 2.5v (page 4 to page 7) as follows: modified common conditions at top of tables from "boldface limits apply over the operating temperature range, -40c to +85c." to "boldface limits apply over the specified operating temperature range." added min/max vos spec from -40c to 125c: 4v updated conditions cell for tcvos fr om +85c to +125c. no limit change. added min/max ibias spec from -40c to 125c: 550pa added typ tcibias spec from -40c to 125c: 2pa/c added min/max ios spec from -40c to 125c: 750pa added typ tcios spec from ta = -40c to +125c: 4pa/c updated conditions cell for common mode input voltage range spec (removed t a = -40c to +85c). no limit change. updated conditions cell for cmrr for over temp (bolded) specs (removed t a = -40c to +85c). no limit change. updated conditions cell for psrr for over temp (bolded) specs (removed t a = -40c to +85c). no limit change. updated conditions cell for vs (removed t a = -40c to +85c). no limit change. added max is spec from -40c to 125c: 1150a updated conditions cell for voh for over temp (bolded) specs (removed t a = -40c to +85c). no limit change. updated conditions cell for vol for ov er temp (bolded) specs (removed t a = -40c to +85c). no limit change. updated the following figures to reflect the temp range from the range of (-40c to 85c) to (-40c to 125c) figures 3-8, page 7 to page 8 figures 11-20, page 8 to page 10 minor edit to spice netlist figure 49, page 18. added ?+? signs on 3 rows as follows: ?model pmosisil pmos (kp=16e-3 vto=-0.6 +kf=0 af=1) .model nchannelmosfet nmos (kp=3e-3 +vto=0.6 kf=0 af=1) .model dn d(kf=6.69e-9 af=1) .model dx d(is=1e-12 rs=0.1 kf=0 af=1) .model dy d(is=1e-15 bv=50 rs=1 kf=0 +af=1) .ends isl28134? july 6, 2011 fn6957.2 added evaluation board to ?ordering information? on page 3. updated ?input noise voltage density vs frequency? on page 10 (changed min frequency from 100mhz to 1mhz) updated ?large signal step response (3v)? on page 13 by changing the time from 0 to 10 to 0 to 20 added ?isl28134 spice model? section, which includes schematic, macromodel and characterization vs simulation results. june 8, 2011 fn6957.1 initial release to web.
fn6957 rev 6.00 page 23 of 25 october 14, 2014 isl28134 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2011-2014. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support
isl28134 fn6957 rev 6.00 page 24 of 25 october 14, 2014 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise s pecified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side . dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view a typical recomme nded land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view b
isl28134 fn6957 rev 6.00 page 25 of 25 october 14, 2014 package outline drawing p5.064a 5 lead small outline tra nsistor plastic package rev 0, 2/10 dimension is exclusive of mold flash, protrusions or gate burrs . this dimension is measured at datum h. package conforms to jedec mo-178aa. foot length is measured at r eference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 1.60 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 0.08-0.20 see detail x 1.45 max (0.60) 0-3 c b a d 3 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 5 2 4 5 5 end view plane

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